Profile shaping for control gate recesses

ABSTRACT

Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 Å

TECHNICAL FIELD

The present technology relates to semiconductor processes and materials.More specifically, the present technology relates to methods of formingcontrol gate recesses with a substantially straight profile.

BACKGROUND

Integrated circuits are made possible by processes which produceintricately patterned material layers on substrate surfaces. Producingpatterned material on a substrate requires controlled methods offormation and removal of exposed material. Stacked memory, such asvertical or 3D NAND, may include the formation of a series ofalternating layers of dielectric and semiconductor materials throughwhich a number of memory holes or apertures may be etched. Materialproperties of the layers, as well as process conditions and materialsfor etching, may affect the uniformity and integrity of the formedstructures. As devices continue to scale, conventional technologies maybe incapable of adequate processing.

Thus, there is a need for improved systems and methods that can be usedto produce high quality devices and structures. These and other needsare addressed by the present technology.

SUMMARY

The present technology includes embodiments of semiconductor processingmethods to form and etch a semiconductor layer with substantiallystraight profile for a recessed surface. In embodiments, thesemiconductor layer may be formed with increased etch resistance in themiddle of the layer compared to the ends of the layer. This etchresistance profile counters a tendency of dry etching operations to etchthe middle of the semiconductor layer at a faster rate than the ends ofthe layer that are in contact with adjacent layers made from othermaterials. When embodiments of the present semiconductor layer isetched, the profile of the recessed surface of the layer may becharacterized by substantially less concavity than a conventionalsemiconductor layer having a substantially uniform etch resistanceacross the depth of the layer. Applications of the present technologyinclude the formation of control gate recesses in multilayeroxide-polysilicon stacks used in floating-gate 3D-NAND devices.

Embodiments of the present technology include semiconductor processingmethods that include forming a first portion of a first semiconductorlayer characterized by a first etch rate for an etch treatment.Embodiments of the method further include forming a second portion ofthe first semiconductor layer characterized by a second etch rate thatis less than the first etch rate for the etch treatment. In embodiments,the method may further include forming a third portion of the firstsemiconductor layer characterized by a third etch rate that is greaterthan the second etch rate. The method may still further include etchingan opening through the first semiconductor layer, where the opening hasa height and width. The opening may be characterized by a variation inthe width between a midpoint of the height of the opening and anendpoint of the opening that is less than or about 5 Å.

In additional embodiments, the first semiconductor layer may includepolysilicon, and may be formed between two dielectric layers. In furtherembodiments, the dielectric layers may be formed from silicon oxide. Instill further embodiments, the second portion of the first semiconductorlayer may be characterized by a greater atomic percentage of phosphorousthan the first portion or the third portion of the semiconductor layer.In yet additional embodiments, the second portion of the firstsemiconductor layer may be characterized by a higher amount of stressthan the first portion or the third portion of the semiconductor layer.In still additional embodiments, the method may further include forminga second semiconductor layer after the formation of the firstsemiconductor layer. The second semiconductor layer may have an averageetch rate for the etch treatment that is less than an average etch ratefor the first semiconductor layer. In embodiments, the secondsemiconductor layer may have at least three portions characterized bydifferent etch rates for the etch treatment.

The present technology may further include semiconductor processingmethods that include flowing deposition precursors into a substrateprocessing region of a semiconductor processing chamber. In embodiments,the deposition precursors may include a silicon-containing precursor anda doping precursor. The deposition precursors may deposit a firstportion of a doped polysilicon layer on a substrate in the substrateprocessing region of the semiconductor processing chamber. Following thedeposition of the first portion of the doped polysilicon layer, a flowrate ratio of the doping precursor to the silicon-containing precursormay be increased. The deposition precursors with the changed flow rateratio may deposit a second portion of a doped polysilicon layer on thesubstrate. The second portion may be characterized by a lower etch ratefor an etch treatment than the first portion of the doped polysiliconlayer. The method may further include decreasing a flow rate ratio ofthe doping precursor to the silicon-containing precursor and depositinga third portion of the doped polysilicon layer on the substrate with thedeposition precursors. The third portion of the polysilicon layer may becharacterized by a higher etch rate for the etch treatment than thesecond portion of the doped polysilicon layer.

In additional embodiments, the silicon-containing precursor may includesilane (SiH₄). In still further embodiments, the doping precursor mayinclude a phosphorous-containing precursor. In yet further embodiments,the method may include etching an opening through the doped polysiliconlayer. The opening has a height and a width, and may be characterized bya variation in the width between a midpoint of the height of the openingand an endpoint of the opening that is less than or about 5 Å. Inadditional embodiments, the substrate may include a first dielectriclayer upon which the first portion of the doped polysilicon layer may bedeposited. In still additional embodiments, the method may includedepositing a second dielectric layer on the doped polysilicon layer.

The present technology may also include embodiments of semiconductorstructures. In embodiments, these structures may include at least onepair of layer that include a dielectric layer and a semiconductor layer.In further embodiments, the semiconductor layer may include a firstportion characterized by a first etch rate for an etch treatment, asecond portion that is characterized by a second etch rate that is lessthan the first etch rate, and a third portion of the semiconductor layerthat is characterized by a third etch rate that is greater than thesecond etch rate.

In additional embodiments, the dielectric layer may include siliconoxide. The yet further embodiments, the semiconductor layer may includedoped polysilicon. In still additional embodiments, the second portionof the semiconductor layer may be characterized by a greater atomicpercentage of phosphorous than the first portion or third portion of thesemiconductor layer. In yet further embodiments, the second portion ofthe semiconductor layer may be characterized by a higher amount ofstress than the first portion or the third portion of the semiconductorlayer. In yet additional embodiments, the at least one pair of layers inthe semiconductor structure may be greater than or about 50 pairs oflayers.

Such technology may provide numerous benefits over conventionalsemiconductor processing methods and structures. For example, themethods may produce films characterized by straighter recessed edgeprofiles in an etch semiconductor layer. Additionally, the operations ofembodiments of the present technology may produce semiconductor devices,such as floating-gate 3D-NAND devices, with reduced critical dimensionsresulting from more precision in the profiles of the control gates.These and other embodiments, along with many of their advantages andfeatures, are described in more detail in conjunction with the belowdescription and attached figures.

BRIEF DESCRIPTION OF THE DRAWINGS

A further understanding of the nature and advantages of the disclosedtechnology may be realized by reference to the remaining portions of thespecification and the drawings.

FIG. 1 shows a top plan view of one embodiment of an exemplaryprocessing system according to some embodiments of the presenttechnology.

FIG. 2A shows a schematic cross-sectional view of an exemplaryprocessing chamber according to some embodiments of the presenttechnology.

FIG. 2B shows a schematic cross-sectional view of an exemplaryprocessing chamber according to some embodiments of the presenttechnology.

FIG. 3 shows exemplary operations in a method of forming a semiconductorstructure according to some embodiments of the present technology.

FIGS. 4A-4D show schematic cross-sectional views of a substrate duringformation operations according to some embodiments of the presenttechnology.

FIG. 5 shows schematic cross-sectional views of a substrate duringformation operations according to additional embodiments of the presenttechnology.

Several of the figures are included as schematics. It is to beunderstood that the figures are for illustrative purposes, and are notto be considered of scale unless specifically stated to be of scale.Additionally, as schematics, the figures are provided to aidcomprehension and may not include all aspects or information compared torealistic representations, and may include exaggerated material forillustrative purposes.

In the appended figures, similar components and/or features may have thesame reference label. Further, various components of the same type maybe distinguished by following the reference label by a letter thatdistinguishes among the similar components. If only the first referencelabel is used in the specification, the description is applicable to anyone of the similar components having the same first reference labelirrespective of the letter.

DETAILED DESCRIPTION

The present technology includes semiconductor processing systems,structures, and methods to form a substantially straight recessedsurface in a semiconductor layer positioned between dielectric layers.In embodiments, the recessed surface may form part of a recess that hasbeen etched into an end of the semiconductor layer starting from anchannel opening that is orthogonally-aligned with the layer. Thedielectric layers positioned between the semiconductor layer may formopposite sides of the recess that are substantially perpendicular to therecessed surface. In embodiments, a series of these recesses may beformed in a series of semiconductor layers along a length of theorthogonally-aligned channel opening. In subsequent operations, therecesses may be filed with materials to form a floating-gate portion ofa control gate. The substantially straight recessed surface etched intothe semiconductor layers may define the shape of an interface betweenthe floating-gate portion and the remainder of the control gate. Inembodiments, the series of control gates formed along the length of thechannel opening may be part of a floating-gate, 3D-NAND memory device.

Embodiments of the present technology address problems with conventionalmethods of etching recessed surfaces in semiconductor layers. In manyconventional methods the etch treatment etches the recess unevenlybetween the middle of the semiconductor layer and the ends of the layerthat make contact with the adjacent dielectric layers. The unevenetching usually involves a faster etch rate for the semiconductormaterial in the middle of the layer compared to the etch rates at theends of the layer. Consequently, the recessed surface is formed with aconcave shape that is etched deeper in the middle of the layer than atthe ends of the layer. In some instances, the difference in the depth ofthe recessed surface between the middle of the surface and one of theends of the surface may be greater than or about 10 Å, greater than orabout 12.5 Å, greater than or about 15 Å, greater than or about 17.5 Å,greater than or about 20 Å, greater than or about 22.5 Å, greater thanor about 25 Å, greater than or about 27.5 Å, greater than or about 30 Å,or more. The larger the difference in this depth (i.e., the greater theextent of the concavity in the recessed surface) the greater the amountof space required for the control gate. As device size continues to bereduced in applications such as 3D-NAND memory devices, the concavity inthe recessed surfaces of the control gate can limit further sizereductions.

Embodiments of the present technology address these and other problemsin the formation of recessed surfaces of semiconductor layer by formingthe layers with different etch rates in different portions of the layer.In embodiments, the tendency of an etch treatment to etch the middle ofa semiconductor layer faster than the of the layer is countered byforming the layer with an increased etch resistance in the middle of thelayer compared to the ends of the layer. In some embodiments, thedifferent etch rates are created in the layer by changing one or morecompositional or physical characteristic of different portions of thelayer. In embodiments, the middle of the semiconductor layer may have amole percentage of a doping material that is greater than the endos ofthe layer. The doping material is selected to impart increased etchresistance to the semiconductor layer with an increasing mole percentageof the doping material. In additional embodiments, the middle of thesemiconductor layer may have a higher amount of stress than the ends ofthe layer. An increased amount of stress imparts an increased etchresistance to the semiconductor layer. In further embodiments, as theeffects of increased etch rate of the etch treatment and the increasedetch resistance of the portion of the semiconductor layer balance eachother out to create an etch front with substantially the same etch rateat all points along the recessing surface. Consequently, the recessedsurface formed in the semiconductor layer is substantially straight. Inembodiments, the difference in the depth of the recessed surface betweenthe middle of the surface and one of the ends of the surface may be lessthan or about 5 Å, less than or about 4 Å, less than or about 3 Å, lessthan or about 2 Å, less than or about 1 Å, or less.

Although the remaining disclosure will routinely identify specificdeposition and removal processes utilizing the disclosed technology toproduce specific structures, such as for memory, it will be readilyunderstood that the systems and methods are equally applicable to anumber of other processes and semiconductor structures. Accordingly, thetechnology should not be considered to be so limited as for use with thenoted deposition and etching processes or chambers alone. Moreover,although an exemplary chamber and system is described to providefoundation for the present technology, it is to be understood that thepresent technology can be applied to virtually any semiconductorprocessing chamber or system that may allow the processing operationsdescribed.

FIG. 1 shows a top plan view of one embodiment of a processing system100 of deposition, etching, annealing, or other processing chambersaccording to embodiments. In the figure, a pair of front opening unifiedpods 102 supply substrates of a variety of sizes that are received byrobotic arms 104 and placed into a low pressure holding area 106 beforebeing placed into one of the substrate processing chambers 108 a-f,positioned in tandem sections 109 a-109 c. A second robotic arm 110 maybe used to transport the substrate wafers from the holding area 106 tothe substrate processing chambers 108 a-f and back. Each substrateprocessing chamber 108 a-f, can be outfitted to perform a number ofsubstrate processing operations including deposition processes describedherein in addition to dry etching processes, removal processing, atomiclayer deposition, chemical vapor deposition, physical vapor deposition,general etch, pre-clean, degas, orientation, and other substrateprocesses.

The substrate processing chambers 108 a-f may include one or more systemcomponents for depositing, annealing, curing and/or etching a dielectricfilm on the substrate wafer. In one configuration, two pairs of theprocessing chambers, e.g., 108 c-d and 108 e-f, may be configuredspecifically to deposit dielectric material on the substrate asdescribed below, and the third pair of processing chambers, e.g., 108a-b, may be used to etch the deposited dielectric. In anotherconfiguration, all three pairs of chambers, e.g., 108 a-f, may beconfigured to deposit a dielectric film on the substrate. Any one ormore of the processes described may be carried out in one or morechambers separated from the fabrication system shown in differentembodiments. It will be appreciated that additional configurations ofdeposition, etching, annealing, and curing chambers for dielectric filmsare contemplated by system 100.

FIG. 2A shows a cross-sectional view of an exemplary processing chamber200 according to some embodiments of the present technology. The figuremay illustrate an overview of a system incorporating one or more aspectsof the present technology, and/or which may be specifically configuredto perform one or more operations according to embodiments of thepresent technology. Additional details of chamber 200 or methodsperformed in the specifically configured chamber may be describedfurther below. Chamber 200 may be utilized to form film layers accordingto some embodiments of the present technology, although it is to beunderstood that the methods may similarly be performed in any chamberwithin which film formation may occur. The processing chamber 200 mayinclude a chamber body 202, a substrate support 204 disposed inside thechamber body 202, and a lid assembly 206 coupled with the chamber body202 and enclosing the substrate support 204 in a processing volume 220.A substrate 203 may be provided to the processing volume 220 through anopening 226, which may be conventionally sealed for processing using aslit valve or door. The substrate 203 may be seated on a surface 205 ofthe substrate support during processing. The substrate support 204 maybe rotatable, as indicated by the arrow 245, along an axis 247, where ashaft 244 of the substrate support 204 may be located. Alternatively,the substrate support 204 may be lifted up to rotate as necessary duringa deposition process.

A plasma profile modulator 211 may be disposed in the processing chamber200 to control plasma distribution across the substrate 203 disposed onthe substrate support 204. The plasma profile modulator 211 may includea first electrode 208 that may be disposed adjacent to the chamber body202, and may separate the chamber body 202 from other components of thelid assembly 206. The first electrode 208 may be part of the lidassembly 206, or may be a separate sidewall electrode. The firstelectrode 208 may be an annular or ring-like member, and may be a ringelectrode. The first electrode 208 may be a continuous member around acircumference of the processing chamber 200 surrounding the processingvolume 220, or may be discontinuous at selected locations if desired.The first electrode 208 may also be a perforated electrode, such as aperforated ring or a mesh electrode, or may be a plate electrode, suchas, for example, a secondary gas distributor.

One or more isolators 210 a, 210 b, which may be a dielectric materialsuch as a ceramic or metal oxide, for example aluminum oxide and/oraluminum nitride, may contact the first electrode 208 and separate thefirst electrode 208 electrically and thermally from a gas distributor212 and from the chamber body 202. The gas distributor 212 may defineapertures 218 for distributing process precursors into the processingvolume 220. The gas distributor 212 may be coupled with a first sourceof electric power 242, such as an RF generator, RF power source, DCpower source, pulsed DC power source, pulsed RF power source, or anyother power source that may be coupled with the processing chamber. Insome embodiments, the first source of electric power 242 may be an RFpower source. In some embodiments the first source of electric power 242may also be an inductively coupled plasma coil extending about inlet214, and which may be used to produce or deliver plasma effluents intothe processing volume 220.

The gas distributor 212 may be a conductive gas distributor or anon-conductive gas distributor. The gas distributor 212 may also beformed of conductive and non-conductive components. For example, a bodyof the gas distributor 212 may be conductive while a face plate of thegas distributor 212 may be non-conductive. The gas distributor 212 maybe powered, such as by the first source of electric power 242 as shownin FIG. 2, or the gas distributor 212 may be coupled with ground in someembodiments.

The first electrode 208 may be coupled with a first tuning circuit 228that may control a ground pathway of the processing chamber 200. Thefirst tuning circuit 228 may include a first electronic sensor 230 and afirst electronic controller 234. The first electronic controller 234 maybe or include a variable capacitor or other circuit elements. The firsttuning circuit 228 may be or include one or more inductors 232. Thefirst tuning circuit 228 may be any circuit that enables variable orcontrollable impedance under the plasma conditions present in theprocessing volume 220 during processing. In some embodiments asillustrated, the first tuning circuit 228 may include a first circuitleg and a second circuit leg coupled in parallel between ground and thefirst electronic sensor 230. The first circuit leg may include a firstinductor 232 a. The second circuit leg may include a second inductor 232b coupled in series with the first electronic controller 234. The secondinductor 232 b may be disposed between the first electronic controller234 and a node connecting both the first and second circuit legs to thefirst electronic sensor 230. The first electronic sensor 230 may be avoltage or current sensor and may be coupled with the first electroniccontroller 234, which may afford a degree of closed-loop control ofplasma conditions inside the processing volume 220.

A second electrode 222 may be coupled with the substrate support 204.The second electrode 222 may be embedded within the substrate support204 or coupled with a surface of the substrate support 204. The secondelectrode 222 may be a plate, a perforated plate, a mesh, a wire screen,or any other distributed arrangement of conductive elements. The secondelectrode 222 may be a tuning electrode, and may be coupled with asecond tuning circuit 236 by a conduit 246, for example a cable having aselected resistance, such as 50 ohms, for example, disposed in the shaft244 of the substrate support 204. The second tuning circuit 236 may havea second electronic sensor 238 and a second electronic controller 240,which may be a second variable capacitor. The second electronic sensor238 may be a voltage or current sensor, and may be coupled with thesecond electronic controller 240 to provide further control over plasmaconditions in the processing volume 220.

A third electrode 224, which may be a bias electrode and/or anelectrostatic chucking electrode, may be coupled with the substratesupport 204. The third electrode may be coupled with a second source ofelectric power 250 through a filter 248, which may be an impedancematching circuit. The second source of electric power 250 may be DCpower, pulsed DC power, RF bias power, a pulsed RF source or bias power,or a combination of these or other power sources. In some embodiments,the second source of electric power 250 may be an RF bias power.

The lid assembly 206 and substrate support 204 of FIG. 1 may be usedwith any processing chamber for plasma or thermal processing. Inoperation, the processing chamber 200 may afford real-time control ofplasma conditions in the processing volume 220. The substrate 203 may bedisposed on the substrate support 204, and process gases may be flowedthrough the lid assembly 206 using inlet 214 according to any desiredflow plan. Gases may exit the processing chamber 200 through an outlet252, which may be coupled with a pump, such as any exhaust pump,including a turbomolecular pump in some embodiments. Electric power maybe coupled with the gas distributor 212 to establish a plasma in theprocessing volume 220. The substrate may be subjected to an electricalbias using the third electrode 224 in some embodiments.

Upon energizing a plasma in the processing volume 220, a potentialdifference may be established between the plasma and the first electrode208. A potential difference may also be established between the plasmaand the second electrode 222. The electronic controllers 234, 240 maythen be used to adjust the flow properties of the ground pathsrepresented by the two tuning circuits 228 and 236. A set point may bedelivered to the first tuning circuit 228 and the second tuning circuit236 to provide independent control of deposition rate and of plasmadensity uniformity from center to edge. In embodiments where theelectronic controllers may both be variable capacitors, the electronicsensors may adjust the variable capacitors to maximize deposition rateand minimize thickness non-uniformity independently.

Each of the tuning circuits 228, 236 may have a variable impedance thatmay be adjusted using the respective electronic controllers 234, 240.Where the electronic controllers 234, 240 are variable capacitors, thecapacitance range of each of the variable capacitors, and theinductances of the first inductor 232 a and the second inductor 232 b,may be chosen to provide an impedance range. This range may depend onthe frequency and voltage characteristics of the plasma, which may havea minimum in the capacitance range of each variable capacitor. Hence,when the capacitance of the first electronic controller 234 is at aminimum or maximum, impedance of the first tuning circuit 228 may behigh, resulting in a plasma shape that has a minimum aerial or lateralcoverage over the substrate support. When the capacitance of the firstelectronic controller 234 approaches a value that minimizes theimpedance of the first tuning circuit 228, the aerial coverage of theplasma may grow to a maximum, effectively covering the entire workingarea of the substrate support 204. As the capacitance of the firstelectronic controller 234 deviates from the minimum impedance setting,the plasma shape may shrink from the chamber walls and aerial coverageof the substrate support may decline. The second electronic controller240 may have a similar effect, increasing and decreasing aerial coverageof the plasma over the substrate support as the capacitance of thesecond electronic controller 240 may be changed.

The electronic sensors 230, 238 may be used to tune the respectivecircuits 228, 236 in a closed loop. A setpoint for current or voltage,depending on the type of sensor used, may be installed in each sensor,and the sensor may be provided with control software that determines anadjustment to each respective electronic controller 234, 240 to minimizedeviation from the setpoint. Consequently, a plasma shape may beselected and dynamically controlled during processing. It is to beunderstood that, while the foregoing discussion is based on electroniccontrollers 234, 240, which may be variable capacitors, any electroniccomponent with adjustable characteristic may be used to provide tuningcircuits 228 and 236 with adjustable impedance.

FIG. 2B is a schematic cross-sectional view of a plasma chamber 260according to some embodiments of the present technology. The figure mayillustrate an overview of a system incorporating one or more aspects ofthe present technology, and/or which may be specifically configured toperform one or more operations according to embodiments of the presenttechnology, such as utilizing an inductively-coupled plasma source. Whenutilizing a chamber incorporating an inductively-coupled plasma,additional plasma parameters may be controlled, which may affect filmsproduced. For example, the chamber may afford lower processingpressures, which may impact film formation and properties. Plasmachamber 260 may include a chamber body 262 and lid assembly 264, whichmay be coupled with the chamber body. The lid assembly 264 may include aprecursor delivery assembly 266 and a lid 268. The lid 268 may define anaperture or opening 270, which may provide access for one or moreprocessing precursor gases within the processing chamber.

The precursor delivery assembly 266 may be disposed over the lid 268 andextending through the opening 270. The precursor delivery assembly 266may be coupled with a precursor source 272, and which may provideprecursors through an inlet 274 to supply one or more processingprecursors into a substrate processing region 275. A substrate 276 maybe disposed on a substrate support 278 positioned within or extendinginto the substrate processing region 275 and coupled with a bias powersource or other material or electrical components. The one or moreprocessing precursor gases may exit the substrate processing region 275via an exhaust ring 280, which may be coupled with an exhaust pump 282.In some embodiments, pump 282 may be a turbo molecular pump, which mayallow operational pressures below or about 1 Torr, below or about 500mTorr, below or about 100 mTorr, below or about 50 mTorr, below or about20 mTorr, below or about 5 mTorr, or less.

Coupled with the lid assembly 264 may be one or more coils forenergizing precursors to produce plasma effluents. The coils may includea number of coil sets, such as inner coils 284, middle coils 286, andouter coils 288, which may all be disposed proximate the lid 268, andmay extend about opening 270, for example. The inner coils 284 and theouter coils 288 may be electrically coupled with an RF power source 290through a matching circuit 292. Power applied to the outer coils 446from the RF power source 290 may be inductively coupled through the lid268 to generate plasma from the processing precursors provided from theprecursor source 272 within the substrate processing region 275. The RFpower source 290 may provide current at a number of differentfrequencies to control the plasma density, such as a number of ions perunit volume in the plasma, which may define a density of ion fluxcorresponding to the plasma density over time. The bias power source maycontrol a voltage between the substrate 276 and the plasma produced, andmay therefore control an energy and directionality of the ions, such asto draw them towards the substrate. Consequently, plasma chamber 260 mayindependently control both ion flux and ion energy.

A heater assembly 294 may be positioned adjacent the lid 268, and insome embodiments may be positioned between the lid and the coils asillustrated. The heater assembly 294 may be secured to the lid 408 withclamping members 296. A surface of the substrate may be maintained at arange of temperatures, which may extend between about 100° C. and about500° C. or more. Plasma chamber 260 may be used in any number ofembodiments to produce films as described further below.

FIG. 3 shows exemplary operations in a processing method 300 accordingto some embodiments of the present technology. The method may beperformed in a variety of processing chambers, including processingchamber 200 described above, which may be incorporated on system 100,for example. Method 300 may include a number of optional operations,which may or may not be specifically associated with some embodiments ofmethods according to the present technology. For example, many of theoperations are described in order to provide a broader scope of thestructural formation, but are not critical to the technology, or may beperformed by alternative methodology as would be readily appreciated.Method 300 may describe operations shown schematically in FIGS. 4A-4D,the illustrations of which will be described in conjunction with theoperations of method 300. It is to be understood that the figuresillustrate only partial schematic views, and a substrate may contain anynumber of structural sections having aspects as illustrated in thefigures, as well as alternative structural aspects that may stillbenefit from operations of the present technology.

Method 300 may include additional operations prior to initiation of thelisted operations. For example, additional processing operations mayinclude forming structures on a semiconductor substrate, which mayinclude both forming and removing material. Prior processing operationsmay be performed in the chamber in which method 300 may be performed, orprocessing may be performed in one or more other processing chambersprior to delivering the substrate into the semiconductor processingchamber in which method 300 may be performed. Regardless, method 300 mayoptionally include delivering a semiconductor substrate to a processingregion of a semiconductor processing chamber, such as processing chamber200 described above, or other chambers that may include components asdescribed above. The substrate may be deposited on a substrate support,which may be a pedestal such as substrate support 204, and which mayreside in a processing region of the chamber, such as processing volume220 described above. An exemplary substrate 411 is illustrated in FIG.4A, and may be or include aspects of a substrate on which operationsaccording to the present technology may be performed.

The substrate 411 may be any number of materials on which materials maybe deposited. The substrate may be or include silicon, germanium,dielectric materials including silicon oxide or silicon nitride, metalmaterials, or any number of combinations of these materials, which maybe the substrate 411, or materials formed on substrate 411. In someembodiments optional treatment operations, such as a pretreatment, maybe performed to prepare a surface of substrate 411 for deposition.Additionally, material removal may be performed, such as reduction ofnative oxides or etching of material, or any other operation that mayprepare one or more exposed surfaces of substrate 411 for deposition.

In the embodiment shown in FIGS. 4A-4D, a first dielectric layer 413 maybe formed on the substrate 411. In further embodiments, the firstdielectric layer 413 may be a silicon oxide layer. The dielectric layer413 may be formed from a silicon-containing precursor and/or anoxygen-containing precursor.

In embodiments, a semiconductor layer 415 may be formed on thedielectric layer 413. The dielectric layer 415 may be characterized by agradient of etch resistance to an etch treatment that includes a peaketch resistance in the middle of the layer and lower etch resistances atthe opposite ends of layer that are closest to and furthest from thedielectric layer 413. In embodiments, this etch resistance profile ofthe semiconductor layer 415 may counter an etch treatment that etchesthe opposite ends of the semiconductor layer at a higher rate than themiddle of the layer. In embodiments, the counterbalancing of the etchrate of the etch treatment and the etch resistance profile of thesemiconductor layer 415 creates an etch profile in the recessedsemiconductor layer that is substantially straight with little or noconcavity.

In embodiments of the present technology, the gradient of etchresistance in the semiconductor layer 415 may be created by altering oneor more properties of the layer during deposition. In embodiments, theseproperties may include a gradient of the atomic percentage of a dopantin the layer. In general, a higher atomic percentage of dopant in thesemiconductor layer 415 is correlated with a higher etch resistance toan etch treatment used to recess the layer. In further embodiments,these properties may include a gradient of the amount of stress in thesemiconductor layer 415. In general, a higher stress level in thesemiconductor layer 415 is correlated with a higher etch resistance toan etch treatment used to recess the layer

In embodiments, the semiconductor layer 415 may include a gradient of anatomic percentage of dopant incorporated into the layer. Embodiments ofthe gradient may include a highest atomic percentage of dopant in amiddle portion of the semiconductor layer 415, and lowest percentages ofdopant in opposite end portions of the layer that are closest to andfurthest from the dielectric layer 413. In some embodiments, thegradient may be a continuously changing atomic percentage of dopantthrough a thickness of the semiconductor layer 415, while in additionalembodiments the gradient may include a plurality of portions where eachportion is characterized by substantially the same atomic percentage ofthe dopant in that portion. In further embodiments the plurality ofportions may include a middle portion that includes a middle pointthrough the thickness of the semiconductor layer 415 that may becharacterized by an atomic percentage of dopant that is greater than theatomic percentage of dopant in any other portion of the layer. In yetfurther embodiments, the plurality of portions may include a pair ofopposite end portions that are closest to and furthest from thedielectric layer 413, at least one of which is characterized by a lowestatomic percentage of dopant in the semiconductor layer 415. In stillfurther embodiments, the opposite end portions of the semiconductorlayer 415 may have the same or different atomic percentages of dopant.In embodiments, the plurality of portions may include greater than orabout three portions, greater than or about four portions, greater thanor about five portions, greater than or about six portions, greater thanor about seven portions, greater than or about eight portions, or more.

In additional embodiments, the semiconductor layer 415 may include aplurality of portions that independently may be characterized by agradient of an atomic percentage of dopant or substantially the sameatomic percentage of the dopant in that portion. In some embodiments,the plurality of portions may include at least three portions where amiddle portion of the semiconductor layer 415 is characterized bysubstantially the same atomic percentage of the dopant while oppositeend portions are characterized by gradients of the atomic percentage ofthe dopant.

Method 300 shown in FIG. 3 includes an embodiment of the processingmethods that forms a semiconductor layer 415 from at least threeportions. In embodiments, the first portion of the semiconductor layer415 a may have a lower etch resistance to an etch treatment than asecond portion of the semiconductor layer 415 b. In additionalembodiments, the third portion of the semiconductor layer 415 c, mayalso have a lower etch resistance to an etch treatment that the secondportion of the semiconductor layer 415 b. In still further embodiments,the first and third portions of the semiconductor layer 415 a and 415 cmay have substantially similar etch resistances to the etch treatment.In yet additional embodiments, the first, second, and third portions ofthe semiconductor layer 415 a-c may independently be characterized by agradient of the atomic percentage of the dopant, or by substantially thesame atomic percentage of the dopant.

Embodiments of method 300 include forming a first portion of asemiconductor layer on a substrate in operation 305. As illustrated inFIG. 4A, the first portion of the semiconductor layer 415 a may beformed on the dielectric layer 413 that is present on substrate 411. Inembodiments, the semiconductor layer may be a silicon-containing layersuch as polysilicon. In further embodiments, the semiconductor layer maybe a doped polysilicon layer. In still additional embodiments, the firstand subsequent portions of the semiconductor layer may be formed bychemical vapor deposition of the portions of the layer on the substrate.In embodiments, the chemical vapor deposition may include the generationof a plasma from deposition precursors and the deposition of the firstand subsequent portions of the semiconductor layer from the effluents ofthe deposition plasma.

In further embodiments, deposition of the first and subsequent portionsof the semiconductor layer on the substrate may include flowingdeposition precursors into a substrate processing region of asemiconductor processing chamber where the substrate is present. Thedeposition precursors may include one or more silicon-containingprecursors and one or more doping precursors. In embodiments, thesilicon-containing precursors may includesilicon-and-hydrogen-containing precursors such as silane (SiH₄) anddisilane (Si₂H₆), among other silicon-and-hydrogen-containingprecursors. In further embodiments, the doping precursors may includephosphorous-containing doping precursors such as phosphine (PH₃). Instill further embodiments, the doping precursors may includenitrogen-containing doping precursors such as ammonia (NH₃) and nitrousoxide (N₂O). In still further embodiments, additional depositionprecursors may include carrier gases such as He, Ar, and molecularnitrogen (N₂). Additional deposition precursors may also includemolecular hydrogen (H₂).

In embodiments, the first portion of the semiconductor layer 415 a maybe formed by flowing the deposition precursors in the semiconductorprocessing chamber at a first flow rate ratio of the doping precursorsto the silicon-containing precursors. In further embodiments, this firstflow rate ratio may be lower than a second flow rate ratio used todeposit a second portion of the semiconductor layer. In embodiments, thefirst flow rate ratio of doping precursors to silicon-containingprecursors may be less than or about 1:1, less than or about 1:2, lessthan or about 1:3, less than or about 1:4, less than or about 1:5, lessthan or about 1:6, less than or about 1:7, less than or about 1:8, lessthan or about 1:9, less than or about 1:10, or less. In additionalembodiments, a flow rate of the doping precursors during the depositionof the first portion of the semiconductor layer may be less than orabout 5000 sccm, less than or about 4000 sccm, less than or about 3000sccm, less than or about 2000 sccm, less than or about 1000 sccm, lessthan or about 500 sccm, less than or about 400 sccm, less than or about300 sccm, less than or about 200 sccm, less than or about 100 sccm, orless. In still additional embodiments, a flow rate of thesilicon-containing precursor may be greater than or about 100 sccm,greater than or about 250 sccm, greater than or about 500 sccm, greaterthan or about 750 sccm, greater than or about 1000 sccm, or more. Insome embodiments, the flow rate of the silicon-containing precursor mayremain constant during the deposition of the semiconductor layer. Inadditional embodiments, the flow rate of the silicon-containingprecursor may change with the change in the flow rate ratio of dopingprecursors to silicon-containing precursors. In still additionalembodiments, the flow rate of the silicon-containing precursors may varywhile the flow rate of the dopant precursors remain constant throughoutthe deposition of the semiconductor layer. In yet additionalembodiments, the deposition precursors may further include a carrier gascharacterized by a flow rate greater than or about 500 sccm, greaterthan or about 1000 sccm, greater than or about 1500 sccm, greater thanor about 2000 sccm, or more.

In additional embodiments, the first portion of the semiconductor layer415 a may be formed in a period less than or about 90 seconds, less thanor about 60 seconds, less than or about 45 seconds, greater than orabout 30 seconds, or less. In still further embodiments, the firstportion of the semiconductor layer 415 a may be formed to a thickness ofless than or about 500 Å, less than or about 400 Å, less than or about200 Å, less than or about 100 Å, or less.

Embodiments of method 300 may further include forming a second portionof a semiconductor layer on as substrate in operation 310. Asillustrated in FIG. 4B, the second portion of the semiconductor layer415 b may be formed on the first portion of the semiconductor layer 415a previously deposited on substrate 411. In embodiments, the secondportion of the semiconductor layer 415 b may be formed under similardeposition conditions as the first portion of the semiconductor layer415 a except for a change in the flow rate ratio of the dopingprecursors to the silicon-containing precursors. In embodiments, asecond flow rate ratio of the doping precursors to thesilicon-containing precursors used to deposit the second portion of thesemiconductor layer 415 b may be greater than the first flow rate ratioused to deposit the first portion of the semiconductor layer 415 a. Infurther embodiments, the second flow rate ratio of doping precursors tosilicon-containing precursors may be greater than or about 1:10, greaterthan or about 1:9, greater than or about 1:8, greater than or about 1:7,greater than or about 1:6, greater than or about 1:5, greater than orabout 1:4, greater than or about 1:3, greater than or about 1:2, greaterthan or about 1:1, or more. In additional embodiments, the increase inthe second flow rate ratio compared to the first flow rate ratio may begreater than or about 5%, greater than or about 10%, greater than orabout 15%, greater than or about 20%, greater than or about 30%, greaterthan or about 40%, greater than or about 50%, or more. In embodiments,the change in flow rate ratio of the doping precursors tosilicon-containing precursors between the depositions of the firstportion and second portion of the semiconductor layer 415 a-b may be acontinuous change or may be a stepwise change.

In additional embodiments, a flow rate of the doping precursors duringthe deposition of the second portion of the semiconductor layer may begreater than or about 100 sccm, greater than or about 250 sccm, greaterthan or about 300 sccm, greater than or about 400 sccm, greater than orabout 500 sccm, greater than or about 1000 sccm, or more. In stilladditional embodiments, a flow rate of the silicon-containing precursormay be less than or about 1000 sccm, less than or about 750 sccm, lessthan or about 500 sccm, less than or about 250 sccm, less than or about100 sccm, or less.

In additional embodiments, the second portion of the semiconductor layer415 b may be formed in a period greater than or about 1 second, greaterthan or about 10 seconds, greater than or about 30 seconds, greater thanor about 45 seconds, greater than or about 60 seconds, greater than orabout 90 seconds, or more. In still further embodiments, the secondportion of the semiconductor layer 415 b may be formed to a thickness ofgreater than or about 50 Å, greater than or about 100 Å, greater than orabout 200 Å, greater than or about 300 Å, greater than or about 400 Å,greater than or about 500 Å, greater than or about 1000 Å, or more.

Embodiments of method 300 may still further include forming a thirdportion of a semiconductor layer on a substrate at operation 315. Asillustrated in FIG. 4C, the third portion of the semiconductor layer 415c may be formed on the second portion of the semiconductor layer 415 bpreviously deposited on substrate 411. In embodiments, the third portionof the semiconductor layer 415 c may be formed under similar depositionconditions as the first and second portions of the semiconductor layer415 a-b except for another change in the flow rate ratio of the dopingprecursors to the silicon-containing precursors. In embodiments, a thirdflow rate ratio of the doping precursors to the silicon-containingprecursors used to deposit the second portion of the semiconductor layer415 b may be less than the second flow rate ratio used to deposit thesecond portion of the semiconductor layer 415 b. In further embodiments,the third flow rate ratio of doping precursors to silicon-containingprecursors may be less than or about 1:1, less than or about 1:2, lessthan or about 1:3, less than or about 1:4, less than or about 1:5, lessthan or about 1:6, less than or about 1:7, less than or about 1:8, lessthan or about 1:9, less than or about 1:10, or less. In embodiments, thechange in flow rate ratio of the doping precursors to silicon-containingprecursors between the depositions of the first portion and secondportion of the semiconductor layer 415 a-b may be a continuous change ormay be a stepwise change. In additional embodiments, the decrease in thethird flow rate ratio compared to the second flow rate ratio may begreater than or about 5%, greater than or about 10%, greater than orabout 15%, greater than or about 20%, greater than or about 30%, greaterthan or about 40%, greater than or about 50%, or more. In embodiments,the change in flow rate ratio of the doping precursors tosilicon-containing precursors between the depositions of the secondportion and third portion of the semiconductor layer 415 b-c may be acontinuous change or may be a stepwise change. In some embodiments, thethird flow rate ratio may be the same as the first flow rate ratio.

In additional embodiments, a flow rate of the doping precursors duringthe deposition of the third portion of the semiconductor layer may beless than or about 500 sccm, less than or about 400 sccm, less than orabout 300 sccm, less than or about 200 sccm, less than or about 100sccm, less than or about 50 sccm, or less. In still additionalembodiments, a flow rate of the silicon-containing precursor may begreater than or about 100 sccm, greater than or about 250 sccm, greaterthan or about 500 sccm, greater than or about 750 sccm, greater than orabout 1000 sccm, or more.

In additional embodiments, the third portion of the semiconductor layer415 c may be formed in a period less than or about 90 seconds, less thanor about 60 seconds, less than or about 45 seconds, greater than orabout 30 seconds, or less. In still further embodiments, the thirdportion of the semiconductor layer 415 c may be formed to a thickness ofless than or about 500 Å, less than or about 400 Å, less than or about200 Å, less than or about 100 Å, or less.

In some embodiments of the present technology, different portions of asemiconductor layer may be formed with different stress levels. Thedifferent stress levels may be correlated with different etch rates foreach portion of the layer. In embodiments, an increased stress level inthe deposited portion of the semiconductor layer may be correlated withan increased etch resistance (i.e., lower etch rate) for that portion.In additional embodiments, changing the stress levels of the depositedportions of the semiconductor layer may replace changing the atomicpercentage of a dopant in order to change the etch rate. In furtherembodiments, both the stress level and atomic percentage of a dopant maybe used to form portions of the semiconductor layer characterized bydifferent etch rates.

In embodiments, a portion of the semiconductor layer that includes amidpoint depth of the level may be characterized by a higher level ofstress than portions of the semiconductor layer at the ends of thelevel. Referring to FIGS. 4A-D, embodiments may include the secondportion of the semiconductor layer 415 b being characterized by a higheramount of stress than either the first portion of the level 415 a or thethird portion of the level 415 c. In additional embodiments, thepercentage different in the amount of stress between the second portionand the first or third portions may be greater than or about 5%, greaterthan or about 10%, greater than or about 15%, greater than or about 20%,greater than or about 25%, greater than or about 30%, or more. In stillfurther embodiments, the second portion of the level 415 b may have astress level that is greater than or about 100 MPa, greater than orabout 500 MPa, greater than or about 1 GPa, greater than or about 1.5GPa or more. In yet additional embodiments, the first and third portionsof the semiconductor level 415 a and 415 may have a stress level that isless than or about 1 GPa, less than or about 500 MPa, less than or about100 MPa, less than or about 50 MPa, less than or about 10 MPa, or less.

In embodiments, the pressure within the processing chamber during theformation of the semiconductor layer may be less than or about 30 Torr,and may be less than or about 20 Torr, less than or about 15 Torr, lessthan or about 12 Torr, less than or about 10 Torr, less than or about 8Torr, less than or about 6 Torr, less than or about 5 Torr, less than orabout 4 Torr, less than or about 3 Torr, less than or about 2 Torr, lessthan or about 1 Torr, or less. For some embodiments, such as withprocessing chambers including an inductively-coupled plasma source, andor a turbomolecular pump, processing pressures may be further reduced toless than or about 100 mTorr, less than or about 90 mTorr, less than orabout 80 mTorr, less than or about 70 mTorr, less than or about 60mTorr, less than or about 50 mTorr, less than or about 40 mTorr, lessthan or about 30 mTorr, less than or about 20 mTorr, less than or about10 mTorr, less than or about 5 mTorr, less than or about 2 mTorr, orless.

In embodiments, the temperature of the substrate during of the formationof the semiconductor layer may be above or about 200° C., and may begreater than or about 250° C., greater than or about 300° C., greaterthan or about 350° C., greater than or about 400° C., greater than orabout 450° C., greater than or about 500° C., or higher. A variety ofplasma powers and other chamber conditions may similarly be modifiedduring the formation of the semiconductor layer.

Embodiments of method 300 may also optionally include forming adielectric layer on the deposited semiconductor layer at operation 320.In the embodiment shown in FIG. 4D, the deposited dielectric layer isshown as a second dielectric layer 420 formed over the semiconductorlayer 415. In embodiments, the first and second dielectric layers 413and 420 may be formed by introducing dielectric deposition precursorsinto the substrate processing region of the semiconductor processingchamber. In embodiments, these dielectric deposition precursors mayinclude silicon-containing precursors such as silane (SiH₄), disilane(Si₂H₆), organosilanes, silicon tetrafluoride (SiF₄), silicontetrachloride (SiCl₄), dichlorosilane (SiH₂Cl₂), tetraethylorthosilicate (TEOS), among other silicon-containing precursors. Thedielectric deposition precursors may also include oxygen-containingprecursors used in any operation as described throughout the presenttechnology may include O₂, N₂O, NO₂, O₃, H₂O, as well as any otheroxygen-containing precursors that may be used in silicon oxide filmformation, or other film formation. In some embodiments, the dielectricprecursors may include nitrogen-containing precursors such as N₂, N₂O,NO₂, NH₃, N₂H₂, among other nitrogen-containing precursors. In any ofthe formation operations one or more additional precursors may beincluded, such as inert precursors, which may include Ar, He, Xe, Kr,nitrogen, hydrogen, or other precursors.

In embodiments, the dielectric layers 413 and 420 may be silicon oxidelayers. In additional embodiments, a stoichiometry of the silicon oxidein the layers may be adjusted to increase the layer's properties. Byincreasing the silicon-like properties of the layer, structuralintegrity may be increased relative to other silicon oxide layers. Toincrease the stoichiometric ratio of the formed dielectric layers, insome embodiments dielectric deposition precursor delivery may bemodified from standard silicon oxide deposition conditions. For example,during some processing, the silicon-to-oxide atomic ratio may be up to1:7 in some embodiments. During formation methods according to someembodiments of the present technology, the silicon-to-oxide ratio may beadjusted to less than or about 1:7, and may be adjusted to less than orabout 1:6, less than or about 1:5, less than or about 1:4, less than orabout 1:3, less than or about 1:2, less than or about 1:1, or less. Byproviding a relatively oxygen-starved formation process compared toother formations, the oxygen-to-silicon ratio within the produced filmmay be less than or about 2.0:1, and may be less than or about 1.9:1,less than or about 1.8:1, less than or about 1.7:1, less than or about1.6:1, less than or about 1.5:1, or less.

By increasing the silicon incorporation within the dielectric layer, aYoung's modulus of the modified oxide layer may be increased to greaterthan or about 100 GPa, and may be increased to greater than or about 110GPa, greater than or about 120 GPa, greater than or about 125 GPa,greater than or about 130 GPa, greater than or about 135 GPa, greaterthan or about 140 GPa, greater than or about 145 GPa, greater than orabout 150 GPa, greater than or about 155 GPa, greater than or about 160GPa, or higher. Additionally, the dielectric layer's hardness mayincrease to greater than or about 12 GPa, and may increase to greaterthan or about 13 GPa, greater than or about 14 GPa, greater than orabout 15 GPa, greater than or about 16 GPa, greater than or about 17GPa, or higher.

In embodiments, the dielectric layers 413 and 420 may function toelectrically insulate semiconductor structures formed in thesemiconductor layer 415. In further embodiments, the dielectric layers413 and 420 may be characterized by a leakage current density that canbe maintained at less than or about 1×10⁻⁶ A/cm², less than or about8×10⁻⁷ A/cm², less than or about 5×10⁻⁷ A/cm², less than or about 2×10⁻⁷A/cm², less than or about 1×10⁻⁷ A/cm², less than or about 9×10⁻⁸ A/cm²,less than or about 8×10⁻⁸ A/cm², less than or about 7×10⁻⁸ A/cm², lessthan or about 6×10⁻⁸ A/cm², less than or about 5×10⁻⁸ A/cm², less thanor about 4×10⁻⁸ A/cm², less than or about 3×10⁻⁸ A/cm², less than orabout 2×10⁻⁸ A/cm², less than or about 1.5×10⁻⁸ A/cm², less than orabout 1.2×10⁻⁸ A/cm², less than or about 1×10⁻⁸ A/cm², or less.

In additional embodiments, the dielectric layers 413 and 420 may becharacterized by a breakdown voltage greater than or about 6.0 MV/cm,greater than or about 7.0 MV/cm, greater than or about 7.5 MV/cm,greater than or about 8.0 MV/cm, greater than or about 8.5 MV/cm,greater than or about 9.0 MV/cm, greater than or about 9.5 MV/cm,greater than or about 10.0 MV/cm, greater than or about 10.5 MV/cm,greater than or about 11.0 MV/cm, greater than or about 11.5 MV/cm,greater than or about 12.0 MV/cm, greater than or about 12.5 MV/cm, orhigher. Consequently, the present technology may produce dielectriclayers that may be characterized by strong resistance to deformation andcollapse during wet etch or other removal processes, and that maysubstantially retain improved electrical performance.

Embodiments of method 300 may yet further include etching an openingthrough the semiconductor layer at operation 325. In the embodimentshown in FIG. 4D, the above described portions of the semiconductorlayer 415 are shown as a single layer that may be characterized by ahigher atomic percentage of a dopant in the middle of the layer than inthe ends of the layer that contact the dielectric layers 413 and 420.The opening 422 formed in the semiconductor layer 415 is also formed inthe dielectric layers 413 and 420 that sandwich opposite sides of thesemiconductor layer 415.

In embodiments, the opening 422 etched in the semiconductor layer 415also includes recesses that extend into the regions between thedielectric layers 413 and 420. Each recess may include a pair ofopposite sides that are defined by opposite facing surfaces of thedielectric layers 413 and 420. Each recess may also include a side thatis formed by an etch front of an etching operation that forms therecesses. In embodiments, each of the recesses may be described as anopening itself, with a height that may be measured as the extent thesemiconductor layer 415 has been etch back from the orthogonally-alignedopening 422, and a width that may be measured as the distance betweenthe opposite facing surfaces of dielectric layers 413 and 420.

In further embodiments, the side of these recessed openings formed bythe etch front may be substantially straight with little or no concavitybetween the midpoint and ends of the side. In still further embodiments,the side of these recessed openings formed by the etch front may becharacterized by a variation in the width between the midpoint andeither end of the side that is less than or about 5 Å, less than orabout 4 Å, less than or about 3 Å, less than or about 2 Å, less than orabout 1 Å, or less. The reduction of concavity in the side of therecessed openings formed by the etch front permits a reduction in thesize of a device that includes the interface of the side with anunetched portion of the semiconductor layer 415. This reduction in sizeremoves a limitation on size reduction for devices that include theinterface, and permits an increased device density on the substrate.

In embodiments, the etching operation 325 may include selectivelyetching the semiconductor layer 415 over the adjacent dielectric layers413 and 420. In additional embodiments, the removal of a portion of thesemiconductor layer 415 may include a silicon removal operationperformed with one or more precursors including a fluorine-containingprecursor, and may also include a hydrogen-containing precursor, as wellas one or more additional precursors, which may include an inert ornoble gas, such as helium, argon, or other materials which mayfacilitate the etch process. In some embodiments, one or both of thefluorine-containing precursor or the hydrogen-containing precursor maybe flowed into a remote plasma region of the dry etch processingchamber. For example, the remote plasma region may be fluidly coupledwith a processing region housing the substrate, although the region maybe physically separated, such as by a showerhead, which may operate asan electrode within the remote plasma region. A remote plasma system mayalso be coupled with the chamber externally and provide plasma effluentsinto the chamber.

Plasma effluents of the precursors may be delivered into the processingregion to contact the semiconductor layer 415 and selectively remove aportion of the layer over the adjacent dielectric layers 413 and 420. Inembodiments, processing conditions may be configured in one or more waysto provide a selective etch of silicon relative to oxide, which may becharacterized by a selectivity of greater than or about 100:1. Forexample, the processing chamber, pedestal, or substrate may bemaintained at a temperature of between about 40° C. and about 150° C.during the etching or removal operation, and a pressure within theprocessing chamber may be maintained below or about 12 Torr, forexample. Additionally, in some embodiments flow rates of thefluorine-containing precursor and/or the hydrogen-containing precursormay be modulated, such as to maintain a flow rate ratio between theprecursors.

For example, in some embodiments, the removal may be performed whilemaintaining an atomic flow-rate ratio of hydrogen to fluorine of greaterthan or about 10:1. Such a process may maintain hydrogen terminatedsurfaces, which may allow fluorine to remove silicon selectively overoxide. Exemplary hydrogen-containing precursors may include one or moreprecursors including hydrogen, such as diatomic hydrogen, ammonia,hydrocarbons, or other precursors including hydrogen. Exemplaryfluorine-containing precursors may include one or more precursorsincluding atomic fluorine, diatomic fluorine, bromine trifluoride,chlorine trifluoride, nitrogen trifluoride, hydrogen fluoride,fluorinated hydrocarbons, sulfur hexafluoride, or xenon difluoride, asnon-limiting examples. Subsequent removal of the silicon layers, furtherprocessing may be conducted, including the deposition of floating gatesemiconductor materials in the recessed regions formed by the etchoperation.

In some embodiments of the present technology, additional treatmentoperations may be performed following the etching operation. Inembodiments, an annealing operation may be performed, such as attemperatures greater than or about 700° C., and which may be greaterthan or about 750° C., greater than or about 800° C., greater than orabout 850° C., greater than or about 900° C., or greater. The anneal maybe performed with a heated precursor, such as an inert precursorincluding nitrogen, for example.

In embodiments of the semiconductor structure 400 shown in FIGS. 4A-D,the thicknesses of the layers in structure 400 may be or include rangesof thicknesses to produce memory or other semiconductor structures. Forexample, in some embodiments, the semiconductor layer 415 and thedielectric layers 413 and 420 may be less than or about 100 nm, lessthan or about 90 nm, less than or about 80 nm, less than or about 70 nm,less than or about 60 nm, less than or about 50 nm, less than or about45 nm, less than or about 40 nm, less than or about 35 nm, less than orabout 30 nm, less than or about 25 nm, less than or about 20 nm, lessthan or about 15 nm, less than or about 10 nm, or less. In someembodiments the layers may be substantially the same thickness while inadditional embodiments the layers may have different thicknesses. Insome embodiments the dielectric layers 413 and 420 may have thicknessessufficient to limit crosstalk or leakage between developed cells. Inadditional embodiments, the semiconductor layer 415 may be characterizedby a thickness less than or about the thickness of one or bothdielectric layers 413 and 420.

Additional embodiments of the present technology may includesemiconductor structures having two or more pairs of layers that includea dielectric layer and a semiconductor layer. An embodiment of thesestructures is shown in FIG. 5, which shows a structure 500 that includesmultiple pairs that include a dielectric layer 513 and a semiconductorlayer 515 formed on a substrate 511. In the embodiment shown, an opening522 is formed through the stack of layer pairs. The semiconductor layers515 are recessed back from the opening 522 to form recessed openingsbetween adjacent dielectric layers 513. In embodiments, the number ofpairs of layers 513 and 515 in structure 500, may be greater than orabout 10 pairs, greater than or about 25 pairs, greater than or about 50pairs, greater than or about 100 pairs, greater than or about 200 pairs,or more.

In further embodiments, the side of these recessed openings formed bythe etch front in semiconductor layers 515 may be substantially straightwith little or no concavity between the midpoint and ends of the side.In still further embodiments, the side of these recessed openings formedby the etch front may be characterized by a variation in the widthbetween the midpoint and either end of the side that is less than orabout 5 Å, less than or about 4 Å, less than or about 3 Å, less than orabout 2 Å, less than or about 1 Å, or less. The reduction of concavityin the side of the recessed openings formed by the etch front permits areduction in the size of a device that includes the interface of theside with an unetched portion of the semiconductor layer 515. Thisreduction in size removes a limitation on size reduction for devicesthat include the interface, and permits an increased device density onthe substrate.

In the preceding description, for the purposes of explanation, numerousdetails have been set forth in order to provide an understanding ofvarious embodiments of the present technology. It will be apparent toone skilled in the art, however, that certain embodiments may bepracticed without some of these details, or with additional details.

Having disclosed several embodiments, it will be recognized by those ofskill in the art that various modifications, alternative constructions,and equivalents may be used without departing from the spirit of theembodiments. Additionally, a number of well-known processes and elementshave not been described in order to avoid unnecessarily obscuring thepresent technology. Accordingly, the above description should not betaken as limiting the scope of the technology. Additionally, methods orprocesses may be described as sequential or in steps, but it is to beunderstood that the operations may be performed concurrently, or indifferent orders than listed.

Where a range of values is provided, it is understood that eachintervening value, to the smallest fraction of the unit of the lowerlimit, unless the context clearly dictates otherwise, between the upperand lower limits of that range is also specifically disclosed. Anynarrower range between any stated values or unstated intervening valuesin a stated range and any other stated or intervening value in thatstated range is encompassed. The upper and lower limits of those smallerranges may independently be included or excluded in the range, and eachrange where either, neither, or both limits are included in the smallerranges is also encompassed within the technology, subject to anyspecifically excluded limit in the stated range. Where the stated rangeincludes one or both of the limits, ranges excluding either or both ofthose included limits are also included.

As used herein and in the appended claims, the singular forms “a”, “an”,and “the” include plural references unless the context clearly dictatesotherwise. Thus, for example, reference to “a precursor” includes aplurality of such precursors, and reference to “the layer” includesreference to one or more layers and equivalents thereof known to thoseskilled in the art, and so forth.

Also, the words “comprise(s)”, “comprising”, “contain(s)”, “containing”,“include(s)”, and “including”, when used in this specification and inthe following claims, are intended to specify the presence of statedfeatures, integers, components, or operations, but they do not precludethe presence or addition of one or more other features, integers,components, operations, acts, or groups.

1. A semiconductor processing method comprising: forming a first portionof a first semiconductor layer characterized by a first etch rate for anetch treatment; forming a second portion of the first semiconductorlayer characterized by a second etch rate that is less than the firstetch rate for the etch treatment; forming a third portion of the firstsemiconductor layer characterized by a third etch rate that is greaterthan the second etch rate; and etching an opening through the firstsemiconductor layer, wherein the opening has a height and a width, andwherein the opening is characterized by a variation in the width betweena midpoint of the height of the opening and an endpoint of the openingthat is less than or about 5 Å.
 2. The semiconductor processing methodof claim 1, wherein the first semiconductor layer comprises polysilicon.3. The semiconductor processing method of claim 1, wherein the firstsemiconductor layer is formed between two dielectric layers.
 4. Thesemiconductor processing method of claim 3, wherein the dielectriclayers comprise silicon oxide.
 5. The semiconductor processing method ofclaim 1, wherein the second portion of the first semiconductor layer hasa greater atomic percentage of phosphorous than the first portion orthird portion of the semiconductor layer.
 6. The semiconductorprocessing method of claim 1, wherein the second portion of the firstsemiconductor layer has a higher amount of stress than the first portionor third portion of the semiconductor layer.
 7. The semiconductorprocessing method of claim 1, wherein the processing method furthercomprises forming a second semiconductor layer after the formation ofthe first semiconductor layer, wherein the second semiconductor layerhas an average etch rate for the etch treatment that is less than anaverage etch rate of the first semiconductor layer.
 8. The semiconductorprocessing method of claim 7, wherein the second semiconductor layercomprises at least three portions that have different etch rates for theetch treatment.
 9. A semiconductor processing method comprising: flowingdeposition precursors into a substrate processing region of asemiconductor processing chamber, wherein the deposition precursorscomprise a silicon-containing precursor and a doping precursor;depositing a first portion of a doped polysilicon layer on a substratein the substrate processing region of the semiconductor processingchamber; increasing a flow rate ratio of the doping precursor to thesilicon-containing precursor and depositing a second portion of thedoped polysilicon layer on the substrate, wherein the second portion ofthe polysilicon layer is characterized by a lower etch rate for an etchtreatment than the first portion of the doped polysilicon layer; anddecreasing a flow rate ratio of the doping precursor to thesilicon-containing precursor and depositing a third portion of the dopedpolysilicon layer on the substrate, wherein the third portion of thepolysilicon layer is characterized by a higher etch rate for the etchtreatment than the second portion of the doped polysilicon layer. 10.The semiconductor processing method of claim 9, wherein thesilicon-containing precursor comprises silane.
 11. The semiconductorprocessing method of claim 9, wherein the doping precursor comprises aphosphorous-containing precursor.
 12. The semiconductor processingmethod of claim 9, wherein the method further comprises etching anopening through the doped polysilicon layer, wherein the opening has aheight and a width, and wherein the opening is characterized by avariation in the width between a midpoint of the height of the openingand an endpoint of the opening that is less than or about 5 Å.
 13. Thesemiconductor processing method of claim 9, wherein the substratecomprises a first dielectric layer upon which the first portion of thedoped polysilicon layer is deposited.
 14. The semiconductor processingmethod of claim 13, wherein the method further comprises depositing asecond dielectric layer on the doped polysilicon layer.
 15. Asemiconductor structure comprising: at least one pair of layerscomprising a dielectric layer and a semiconductor layer, wherein thesemiconductor layer comprises: a first portion of the semiconductorlayer characterized by a first etch rate for an etch treatment, a secondportion of the semiconductor layer characterized by a second etch ratethat is less than the first etch rate for the etch treatment, and athird portion of the semiconductor layer characterized by a third etchrate that is greater than the second etch rate.
 16. The semiconductorstructure of claim 15, wherein the dielectric layer comprises siliconoxide.
 17. The semiconductor structure of claim 15, whereinsemiconductor layer comprises doped polysilicon.
 18. The semiconductorstructure of claim 15, wherein the second portion of the semiconductorlayer is characterized by a greater atomic percentage of phosphorousthan the first portion or third portion of the semiconductor layer. 19.The semiconductor structure of claim 15, wherein the second portion ofthe semiconductor layer is characterized by a higher amount of stressthan the first portion or third portion of the semiconductor layer. 20.The semiconductor structure of claim 15, wherein at least one pair oflayers comprises greater than or about 50 pairs of layers.